Emulation systems may comprise hardware components, such as emulation chips and processors, capable of processor-based (e.g., hardware-based) emulation of logic systems, such as integrated circuits (ICs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPU), field-programmable gate arrays (FPGAs), and the like. By executing various forms of programmable logic, the emulation chips may be programmed to mimic the functionality of nearly any logic system design that is undergoing testing and verification. In other words, emulation systems may be used for a functional verification of the logic system design. Processor-based emulation allows logic designers to prototype a logic system design, before a manufacturer expends resources manufacturing a logic system product based on the logic system design. An emulation system may receive a logic system design in a hardware description language (HDL), such as Verilog or VHDL. In the alternative or in addition, the emulation system may receive the logic system design in a proprietary language. The emulation system may also receive a pre-compiled logic system design in a suitable form based on the specification of the emulation system.
To debug a design being emulated, an emulation system may capture signals travelling between various components within the design during an emulation run. For example, the emulation system may capture a signal generated during the emulation run in a net interconnecting two components of the design. Popular debug methodologies rely heavily on analyzing the waveforms of the captured signals. The waveforms visually show, for instance, the binary value indicated by the captured signals or where the captured signals are changing or toggling the binary values. Capturing the signals may also be referred to as capturing waveform data because the captured data may be used by a workstation computer to render the waveforms of the captured signals.
While the conventional emulation technology allows for a concurrent waveform data capture during an emulation run, uploading the captured waveform data to a workstation computer requires the emulation run to pause or stop. Stopping emulation runs to upload captured data may result in a performance penalty. Because the data uploaded may be per cycle and thus, comprehensive, it takes time to process and render. Furthermore, the dedicated capture memory, for example, data capture card (DCC) memory, used by conventional emulation technology to receive waveform data during emulation run does not support operational modes that may not allow an emulation run to stop. An example of such operational mode is a logic analyzer mode, wherein the system is continuously running and data is captured at trigger. In addition, an emulation run may not stop if the design being emulated is interacting with a target external electronic circuit device that cannot be stopped. If the run period of the modes wherein the emulation run cannot be stopped is longer than the corresponding maximum capacity of the DCC memory, there may be a data overflow, and portions of captured data may be overwritten or lost. Conventional emulation technology also does not allow for probing of dynamically added parts of the design being emulated. In other words, conventional emulation technology is confined to probing of portions of an originally compiled design and cannot handle portions of the design that are added during an emulation run.